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preliminary 18-mbit qdr?-ii sram 4-word burst architecture cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document number: 38-05620 rev. ** revised july 23, 2004 features ? separate independent read and write data ports ? supports concurrent transactions ? 250-mhz clock for high bandwidth ? 4-word burst for reducing address bus frequency ? double data rate (ddr) interfaces on both read and write ports (data transferred at 500 mhz) at 250 mhz ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two output clocks (c and c ) account for clock skew and flight time mismatching ? echo clocks (cq and cq ) simplify data capture in high-speed systems ? single multiplexed address input bus latches address inputs for both read and write ports ? separate port selects for depth expansion ? synchronous internally self-timed writes ? available in 8, x9, 18, and 36 configurations ? full data coherency providing most current data ?core v dd = 1.8(+/-0.1v); i/o v ddq = 1.4v to v dd ) ? 15 17 x 1.4 mm 1.0-mm pitch fbga package, 165-ball (11 15 matrix) ? variable drive hstl output buffers ? jtag 1149.1 compatible test access port ? delay lock loop (dll) for accurate data placement configurations cy7c1311bv18?2m x 8 cy7c1911bv18?2m x 9 cy7c1313bv18?1m x 18 cy7c1315bv18?512k x 36 functional description the cy7c1311bv18, cy7c1911bv18, cy7c1313bv18, and cy7c1315bv18 are 1.8v synchronous pipelined srams, equipped with qdr?-ii architecture. qdr-ii architecture consists of two separate ports to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr-ii architecture has separate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common i/o devices. access to each port is accomplished through a common address bus. addresses for read and write addresses are latched on alternate rising edges of the input (k) clock. accesses to the qdr-ii read and write ports are completely independent of one another. in order to maximize data throughput, both read and write ports are equipped with double data rate (ddr) interfaces. each address location is associated with four 8-bit words (cy7c1311bv18) or 9-bit words (cy7c1911bv18) or 18-bit words (cy7c1313bv18) or 36-bit words (cy7c1315bv18) that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both input clocks (k and k and c and c ), memory bandwidth is maximized while simpli- fying system design by eliminating bus ?turn-arounds?. depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c input clocks. writes are conducted with on-chip synchronous self-timed write circuitry.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 2 of 23 logic block diagram (cy7c1311bv18) 512k x 8 array clk a (18:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logic address register reg. reg. reg. 16 19 8 32 8 nws [1:0] v ref write add. decode write reg 16 a (18:0) 19 c c 512k x 8 array 512k x 8 array 512k x 8 array write reg write reg write reg 8 cq cq doff logic block diagram (cy7c1911bv18) 512k x 9 array clk a (18:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps q [8:0] control logic address register reg. reg. reg. 18 19 9 36 9 bws [0] v ref write add. decode write reg 18 a (18:0) 19 c c 512k x 9 array 512k x 9 array 512k x 9 array write reg write reg write reg 9 cq cq doff
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 3 of 23 logic block diagram (cy7c1313bv18) 256k x 18 array clk a (17:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 36 18 18 72 18 bws [1:0] v ref write add. decode write reg 36 a (17:0) 18 c c 256k x 18 array 256k x 18 array 256k x 18 array write reg write reg write reg 18 cq cq doff logic block diagram (cy7c1315bv18) 128k x 36 array clk a (16:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 72 17 36 144 36 bws [3:0] v ref write add. decode write reg 72 a (16:0) 17 c c 128k x 36 array 128k x 36 array 128k x 36 array write reg write reg write reg 36 cq cq doff selection guide 250 mhz 200 mhz 167 mhz unit maximum operating frequency 250 200 167 mhz maximum operating current tbd tbd tbd ma
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 4 of 23 pin configurations cy7c1311bv18 (2m 8)?15 17 fbga 23 4 5 6 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k wps nc/144m nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k nws 0 v ss anca nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 8 91011 nc anc/36m rps cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a nc/144m cy7c1911bv18 (2m 9)?15 17 fbga 23 4 5 6 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nc k wps nc/144m nc nc nc nc nc tdo nc nc d6 nc nc nc tck nc nc a nc/288m k bws 0 v ss anca nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q5 nc v ddq nc nc nc nc q8 a v ddq v ss v ddq v dd v dd q6 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d5 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q7 nc d8 d7 v dd a 8 91011 q0 a nc/36m rps cq a nc nc q4 v ss nc nc d4 nc v ss nc q3 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d2 v ddq nc q2 nc v ddq v ddq nc v ss nc d1 nc tdi tms v ss a nc a nc d3 nc zq nc q1 nc nc d0 nc a nc nc
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 5 of 23 pin configurations (continued) cy7c1313v18 (1m 18)?15 17 fbga 23 4 56 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m nc/36m bws 1 k wps nc/288m q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss anca q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 8 91011 q0 a nc/72m rps cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a c 23 456 7 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 nc/288m nc/72m bws 2 k wps bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss anca q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 nc/36m nc/144m rps cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq v ddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a cy7c1315av18 (512k 36)?15 17fbga
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 6 of 23 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write opera- tions . cy7c1311bv18 ? d [7:0] cy7c1911bv18 ? d [8:0] cy7c1313bv18 ? d [17:0] cy7c1315bv18 ? d [35:0] wps input- synchronous write port select, active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting will deselect the write port. deselecting the write port will cause d [x:0] to be ignored. nws 0 , nws 1 , input- synchronous nibble write select 0, 1 ? active low .(cy7c1311bv18 only ) sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is written into the device nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the same edge as the data. deselecting a nibble write select will cause the corresponding nibble of data to be ignored and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1911bv18 ? bws 0 controls d [8:0] cy7c1313bv18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1315bv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write opera- tions. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (4 arrays each of 512k x 8) for cy7c1311bv18, 2m x 9 (4 arrays each of 512k x 9) for cy7c1911bv18,1m x 18 (4 arrays each of 256k x 18) for cy7c1313bv18 and 512k x 36 (4 arrays each of 128k x 36) for cy7c1315bv18. therefore, only 19 address inputs are needed to access the entire memory array of cy7c1311bv18 and cy7c1911bv18, 18 address inputs for cy7c1313bv18 and 17 address inputs for cy7c1315bv18. these inputs are ignored when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k . when in single clock mode. when the read port is deselected, q [x:0] are automatically tri-stated. cy7c1311bv18 ? q [7:0] cy7c1911bv18 ? q [8:0] cy7c1313bv18 ? q [17:0] cy7c1315bv18 ? q [35:0] rps input- synchronous read port select, active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the c clock. each read access consists of a burst of four sequential transfers. c input- clock positive output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input- clock negative output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 7 of 23 functional overview the cy7c1311bv18, cy7c1911bv18, cy7c1313bv18, cy7c1315bv18 are synchronous pipelined burst srams equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having separate read and write ports, the qdr-ii completely eliminates the need to ?turn-around? the data bus and avoids any possible data contention, thereby simplifying system design. each access consists of four 8-bit data transfers in the case of cy7c1311bv18, four 9-bit data transfers in the case of cy7c1911bv18, four 18-bit data transfers in the case of cy7c1313bv18, and four 36-bit data in the case of cy7c1315bv18 transfers in two clock cycles. accesses for both ports are initiated on the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the output clocks (c and c or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) inputs pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the rising edge of the output clocks (c and c or k and k when in single-clock mode). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1313bv18 is described in the following sections. the same basic descriptions apply to cy7c1311bv18, cy7c1911bv18, and cy7c1315bv18. read operations the cy7c1313bv18 is organized internally as 4 arrays of 256k x 18. accesses are completed in a burst of four sequential 18-bit data words. read operations are initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to address inputs are stored in the read address register. following the next k clock rise, the corresponding lowest order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c the next 18-bit data word is driven onto the q [17:0] . this process continues until all four 18-bit data cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c) of the qdr-ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c ) of the qdr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off - active low . connecting this pin to ground will turn off the dll inside the device. the timings in the dll turned off operation will be different from those listed in this data sheet. more details on this operation can be found in the application note, ?dll operation in the qdr-ii.? tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/36m n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 8 of 23 words have been driven out onto q [17:0] . the requested data will be valid 0.45 ns from the rising edge of the output clock (c or c or (k or k when in single-clock mode)). in order to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes 2 clock cycles to complete. therefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second read request. read accesses can be initiated on every other k clock rise. doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (c and c or k and k when in single-clock mode). when the read port is deselected, the cy7c1313bv18 will first complete the pending read transactions. synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the positive output clock (c). this will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when deselected, the write port will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1313bv18. a write operation is initiated as described in the write opera- tions section above. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1313bv18 can be used with a single clock that controls both the input and output registers. in this mode the device will recognize only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power on. this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1313bv18 operate completely independently of one another. since each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the trans- action on the other port. if the ports access the same location when a read follows a write in successive clock cycles, the sram will deliver the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. read accesses and write access must be scheduled such that one transaction is initiated on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports were deselected, the read port will take priority. if a read was initiated on the previous cycle, the write port will assume priority (since read operations can not be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port will assume priority (since write operations can not be initiated on consecutive cycles). therefore, asserting both port selects active from a deselected state will result in alternating read/write operations being initiated, with the first access being a read. depth expansion the cy7c1313bv18 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port will not affect the other port. all pending transactions (read and write) will be completed prior to the device being deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qdr-ii to simplify data capture on high-speed systems. two echo clocks are generated by the qdr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free running clocks and are synchronized to the output clock of the qdr-ii. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. dll these chips utilize a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. the dll can also be reset by slowing the cycle time of input clocks k and k to greater than 30 ns.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 9 of 23 application example [1] vt = vddq/2 cc# d a k cc# d a k bus m aster (cpu or a sic) sram #1 sram #4 data in data out address rps# wps# bws# source k source k# delayed k delayed k# r = 50 ohms r = 250 ohms r = 250 ohms r p s # w p s # b w s # r p s # w p s # b w s # vt vt vt r r r zq cq/cq# q k# zq cq/cq# q k# clkin/clkin# truth table [2, 3, 4, 5, 6, 7] operation k rps wps dq dq dq dq write cycle: load address on the rising edge of k; input write data on two consecutive k and k rising edges. l-h h [8] l [9] d(a) at k(t+1) d(a + 1) at k (t+1) d(a + 2) at k(t + 2) d(a + 3) at k (t +2) read cycle: load address on the rising edge of k; wait one and a half cycle; read data on two consecutive c and c rising edges. l-h l [9] x q(a) at c (t +1) q(a + 1) at c(t + 2) q(a + 2) at c (t + 2) q(a + 3) at c(t + 3) nop: no operation l-h h h d = x q = high-z d = x q = high-z d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state previous state previous state write cycle descriptions cy7c1311bv18 and cy7c1313bv18) [2, 10] bws 0 / nws 0 bws 1 / nws 1 kk comments l l l?h ? during the data portion of a write sequence : cy7c1311bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1313bv18 ? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence : cy7c1311bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1313bv18 ? both bytes (d [17:0] ) are written into the device. notes: 1. the above application shows four qdr-ii being used. 2. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 3. device will power-up deselected and the outputs in a tri-state condition. 4. ?a? represents address location latched by the devices when transac tion was initiated. a + 1, a + 2, and a +3 represents the address sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is st arted. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. if this signal was low to initiate the previous cycle, this signal becomes a ?don?t care? for this operation. 9. this signal was high on previous k clock rise. initiating c onsecutive read or write operations on consecutive k clock rises i s not permitted. the device will ignore the second read or write request. 10. assumes a write cycle was initiated per the write port cycle description truth table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 and bws 3 can be altered on different portions of a write cycle, as long as t he set-up and hold requirements are achieved.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 10 of 23 l h l?h ? during the data portion of a write sequence : cy7c1311bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1313bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. l h ? l?h during the data portion of a write sequence : cy7c1311bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1313bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. h l l?h ? during the data portion of a write sequence : cy7c1311bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1313bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h l ? l?h during the data portion of a write sequence : cy7c1311bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1313bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. write cycle descriptions cy7c1311bv18 and cy7c1313bv18) (continued) [2, 10] bws 0 / nws 0 bws 1 / nws 1 kk comments write cycle descriptions [2, 10] (cy7c1315bv18) bws 0 bws 1 bws 2 bws 3 kk comments l l l l l?h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l?h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h h l?h ? no data is written into the device during this portion of a write operation. h h h h ? l?h no data is written into the device during this portion of a write operation. write cycle descriptions [2, 10] (cy7c1911bv18) bws 0 kk l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device during this portion of a write operation. h ? l?h no data is written into the device during this portion of a write operation.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 11 of 23 maximum ratings (above which the useful life may be impaired.) storage temperature ................................. ?65c to +150c ambient temperature with power applied .... ?10c to +85c supply voltage on v dd relative to gnd........ ?0.5v to +2.9v dc applied to outputs in high-z .........?0.5v to v ddq + 0.3v dc input voltage [14] ............................ ?0.5v to v ddq + 0.3v current into outputs (low) .........................................20 ma static discharge voltage (mil-std-883, m. 3015)... >2001v latch-up current..................................................... >200 ma operating range range ambient temperature (t a )v dd [15] v ddq [15] com?l 0c to +70c 1.8 0.1v 1.4v to v dd dc electrical characteristics over the operating range [11] parameter description test conditions min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 12 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 13 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [14] v ref + 0.1 v ddq + 0.3 v v il input low voltage [14] ?0.3 v ref ? 0.1 v i x input load current gnd v i v ddq ? 55 a i oz output leakage current gnd v i v ddq, output disabled ? 55 a v ref input reference voltage [16] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 167 mhz tbd ma 200 mhz tbd ma 250 mhz tbd ma i sb1 automatic power-down current max. v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 167 mhz tbd ma 200 mhz tbd ma 250 mhz tbd ma notes: 11. all voltage referenced to ground. 12. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? s. 13. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? s. 14. overshoot: v ih (ac) < v ddq + 0.85v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5v (pulse width less than t cyc /2). 15. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 16. v ref (min.) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 12 of 23 ac electrical characteristics over the operating range parameter description test conditions min. typ. max. unit v ih input high (logic 1) voltage v ref + 0.2 ? ? v v il input low (logic 0) voltage ? ? v ref ? 0.2 v switching characteristics over the operating range [17, 18] cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. t power v dd (typical) to the first access [21] 1 11ms t cyc t khkh k clock and c clock cycle time 4.0 5.25 5.0 6.3 6.0 8.4 ns t kh t khkl input clock (k/k ; c/c ) high 1.6 ? 2.0 2.4 ? ns t kl t klkh input clock (k/k ; c/c ) low 1.6 ?2.0?2.4? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.8 ?2.2?2.7? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.8 0.0 2.2 0.0 2.7 ns set-up times t sa t sa address set-up to k clock rise 0.5 ?0.6?0.7? ns t sc t sc control set-up to clock (k, k ) rise (rps , wps ) 0.5 ?0.6?0.7? ns t scddr t sc double data rate control set-up to clock (k, k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.35 ?0.4?0.5? ns t sd t sd d [x:0] set-up to clock (k/k ) rise 0.35 ?0.4?0.5? ns hold times t ha t ha address hold after clock (k/k ) rise 0.5 ?0.6?0.7? ns t hc t hc control hold after clock (k /k ) rise (rps , wps ) 0.5 ?0.6?0.7? ns t hcddr t hc double data rate control hold after clock (k/k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.35 ?0.4?0.5? ns t hd t hd d [x:0] hold after clock (k/k ) rise 0.35 ?0.4?0.5? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 0.45 ? 0.45 ? 0.50 ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? -0.45 ? -0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.50 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data valid ? 0.30 ? 0.35 ? 0.40 ns t cqdoh t cqhqx echo clock high to data invalid ?0.30 ? ?0.35 ? ?0.40 ? ns t chz t chz clock (c and c ) rise to high-z (active to high-z) [19, 20] ? 0.45 ? 0.45 ? 0.50 ns t clz t clz clock (c and c ) rise to low-z [19, 20] ?0.45 ? ?0.45 ? ?0.50 ? ns notes: 17. all devices can operate at clock frequencies as low as 1 19 mhz. when a part with a maximum frequency above 167 mhz is operat ing at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 18. unless otherwise noted, test conditions assume signal transition time of 2v/ns, timing reference levels of 0.75v, vref = 0.7 5v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 19. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 20. at any given voltage and temperature t chz is less than t clz and t chz less than t co . 21. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 13 of 23 dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 30 30 ns switching characteristics over the operating range [17, 18] (continued) cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. thermal resistance [22] parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w capacitance [22] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v tbd pf c clk clock input capacitance tbd pf c o output capacitance tbd pf ac test loads and waveforms note: 22. tested initially and after any design or process change that may affect these parameters. 1.25v 0.25v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [14] 0.75v under te s t 0.75v device under te s t output v ref v ref output zq zq (a) rq = 250 ? (b) rq = 250 ? 0.75v slew rate = 2v / ns
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 14 of 23 switching waveforms [23, 24, 25] read/write/deselect sequence notes: 23. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 24. output are disabled (high-z) one clock cycle after a nop. 25. in this example, if address a2 = a1,then data q20 = d10 and q2 1 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. k 1 23456 7 k rps wps a q d c c a0 read read write write q00 q03 d10 d11 d12 d13 a1 t kh t khkh t khch t co t doh t kl t cyc t t hc t sa t ha t sd t hd t khch q01 q02 nop nop qx2 a2 t sd t hd don?t care undefined t cqd t clz t t doh t chz sc tt hc sc t t t kl t cyc a3 qx3 d30 d31 d32 d33 q20 q23 q21 q22 cq cq t ccqo t ccqo t cqoh t cqoh khkh kh co t cqdoh
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 15 of 23 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 16 of 23 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system output pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus tristate?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instruction is entered, this bit will directly control the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 17 of 23 note: 26. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [26] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 18 of 23 tap controller block diagram tap electrical characteristics over the operating range [11, 14, 27] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ?5 5 a tap ac switching characteristics over the operating range [28, 29] parameter description min. max. unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns notes: 27. these characteristic pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 28. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 29. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 19 of 23 output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions [29] tap ac switching characteristics over the operating range [28, 29] (continued) parameter description min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo identification register definitions instruction field value description cy7c1311bv18 cy7c1911bv18 cy7c1313bv18 cy7c1315bv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010011011000101 11010011011001101 11010011011010101 11010011011100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register.
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 20 of 23 scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. boundary scan order bit # bump id 06r 16p 26n 37p 47n 57r 68r 78p 89r 911p 10 10p 11 10n 12 9p 13 10m 14 11n 15 9m 16 9n 17 11l 18 11m 19 9l 20 10l 21 11k 22 10k 23 9j 24 9k 25 10j 26 11j 27 11h 28 10g 29 9g 30 11f 31 11g 32 9f 33 10f 34 11e 35 10e 36 10d 37 9e 38 10c 39 11d 40 9c 41 9d 42 11b 43 11c 44 9b 45 10b boundary scan order (continued) bit # bump id
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 21 of 23 46 11a 47 internal 48 9a 49 8b 50 7c 51 6c 52 8a 53 7a 54 7b 55 6b 56 6a 57 5b 58 5a 59 4a 60 5c 61 4b 62 3a 63 1h 64 1a 65 2b 66 3b 67 1c 68 1b 69 3d 70 3c 71 1d 72 2c 73 3e 74 2d 75 2e 76 1e 77 2f 78 3f 79 1g 80 1f 81 3g 82 2g 83 1j 84 2j 85 3k 86 3j 87 2k 88 1k 89 2l boundary scan order (continued) bit # bump id 90 3l 91 1m 92 1l 93 3n 94 3m 95 1n 96 2m 97 3p 98 2n 99 2p 100 1p 101 3r 102 4r 103 4p 104 5p 105 5n 106 5r boundary scan order (continued) bit # bump id
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 22 of 23 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semico nductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failur e may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support system s application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety a pplications, unless pursuant to an express written agreement with cypress. qdr rams and quad data rate rams comprise a new family of products developed by cypress, hitachi, idt,nec, and samsung technology. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1311bv18-250bzc bb165e 15 x 17 x 1.4 mm fbga commercial cy7c1911bv18-250bzc cy7c1313bv18-250bzc cy7c1315bv18-250bzc 200 cy7c1311bv18-200bzc bb165e 15 x 17x 1.4 mm fbga commercial cy7c1911bv18-200bzc cy7c1313bv18-200bzc cy7c1315bv18-200bzc 167 cy7c1311bv18-167bzc bb165e 15 x 17 x 1.4 mm fbga commercial cy7c1911bv18-167bzc cy7c1313bv18-167bzc cy7c1315bv18-167bzc package diagram a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.410.05 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.14 -0.06 165-ball fbga (15 x 17 x 1.40 mm) pkg. outline (0.50 ball dia.) bb165e 51-85195-**
preliminary cy7c1313bv18 cy7c1911bv18 cy7c1311bv18 cy7c1315bv18 document number: 38-05620 rev. ** page 23 of 23 document history page document title: cy7c1311bv18/cy7c1911bv18/cy7c1313bv18/cy7c1315bv18 18-mbit qdr?-ii sram 4-word burst architecture document number: 38-05620 rev. ecn no. issue date orig. of change description of change ** 252474 see ecn syt new data sheet

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